1. Field of the Invention
The present invention relates to a programmable integrated circuit. In particular, the present invention relates to discharging high voltage nodes associated with programming and erasing of a programmable integrated circuit.
2. Discussion of the Related Art
A programmable integrated circuit, such a programmable logic device (xe2x80x9cPLDxe2x80x9d), is programmed or erased during a xe2x80x9cprogramming mode.xe2x80x9d During the programming mode, the programmable integrated circuit is configured by storing appropriate values into the programmable integrated circuit""s non-volatile memory components (e.g., xe2x80x9carchitecture cellsxe2x80x9d). Once programmed, the programmable integrated circuit can be put to functional operations under a xe2x80x9cuser mode.xe2x80x9d
In some programmable integrated circuits, a high voltage is used to store selected values in the architecture cells during programming mode. Typically, nodes in the programmable integrated circuit that are brought to the high voltage have to be discharged before the next operation can be carried out. During discharge, the electric field at the drain terminal of the discharging transistor at the high voltage can be so high that it creates energetic charges (xe2x80x9chot carriersxe2x80x9d) that create an undesirable localized substrate current. The hot carriers can also be injected into the gate oxide of a transistor to cause a threshold voltage shift in the transistor, thereby degrading performance and creating a reliability problem. For a programmable integrated circuit with a large number of high voltage nodes to be discharged, the total current resulting from the many localized substrate currents can cause either the localized substrate voltage of the discharging transistors to be pulled up to positive voltage (thus causing a xe2x80x9csnap-backxe2x80x9d condition), or the global substrate to be pulled up to a positive voltage (thus causing a xe2x80x9clatch-upxe2x80x9d condition). Either condition is detrimental to proper circuit operation and can potentially damage the device. Therefore, the high voltage discharge scheme must be carefully designed to limit the total discharge current.
The present invention provides a method and a discharge circuit for discharging a high voltage node. In one embodiment of the present invention, the discharge circuit includes (a) a current path providing between a high voltage node to a desirable reference voltage level, with the current path conducting a current whose magnitude is limited by a control voltage; (b) a reference circuit that limits the total discharge current when multiple high voltage nodes are discharged; and (c) a reference voltage circuit for generating the control voltage that limits the current. In one embodiment, the current path includes a transistor coupled between the high voltage node and the ground voltage, and the control voltage is provided across the gate and source terminals of the transistor. In one implementation, the reference voltage circuit includes a current source coupled to the transistor in a current mirror configuration.
In one embodiment, the discharge circuit further includes a voltage detection circuit coupled for detecting the voltage at the source terminal of the discharging transistor. In that embodiment, the voltage detection circuit provides an output control signal indicating that the high voltage node is discharged to a voltage level that would allow the next operation to be carried out. Further, the discharge circuit includes an enable circuit latching the output control signal of the voltage detection circuit. The enable circuit allows control signals of functional operations to be propagated, thereby allowing functional operations after the high voltage nodes are discharged.
By limiting the current in the discharge current path under the present invention, threshold shifts, latch-up conditions and other damages or interference with the proper functional operations of the functional circuit resulting from hot carriers in the discharging of high voltage nodes are avoided.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.